Understanding PCB Impedance and Transmission Lines
Characteristic impedance determines how signals propagate along PCB traces and how energy reflects at discontinuities. Mismatched impedance causes reflections, overshoot, undershoot, and signal degradation—critical issues in high-speed digital and RF designs.
PCB transmission lines exist in multiple geometries:
- Microstrip: signal trace above a ground plane, exposed to air or dielectric on one side
- Stripline: signal trace sandwiched between two reference planes (symmetric or asymmetric)
- Coupled traces: two adjacent conductors exhibiting different odd and even mode impedances
Each configuration requires different calculations accounting for trace thickness, width, height above ground, substrate dielectric constant, and trace spacing. The effective dielectric constant—a weighted average of the substrate material and surrounding medium—varies with trace geometry and must be calculated before impedance.
Microstrip Impedance and Effective Dielectric Constant
Microstrip impedance depends on the trace width, height above the reference plane, substrate dielectric constant, and trace thickness. The effective dielectric constant first accounts for fringing effects where the field partly occupies air and partly the substrate.
Ɛ_eff = (Ɛᵣ + 1)/2 + (Ɛᵣ − 1)/2 × √(W/(W + 12H))
Z₀ = (120π/√Ɛ_eff) × ln(4H/(πW_eff))
where W_eff accounts for trace thickness corrections.
Ɛᵣ— Relative permittivity of substrate material (e.g., 4.5 for FR-4)W— Width of the signal traceH— Height of trace above ground plane (substrate thickness for single-layer microstrip)T— Thickness of the conductor (copper layer thickness)Z₀— Characteristic impedance of the transmission lineƐ_eff— Effective dielectric constant accounting for fringing effects
Stripline and Coupled Trace Impedance
Stripline configurations—where traces sit between reference planes—produce different impedance relationships. Coupled traces exhibit distinct odd-mode impedance (currents in opposite directions) and even-mode impedance (currents in the same direction), affecting differential and common-mode signal propagation.
Z₀_stripline = (120π/(2π√Ɛᵣ)) × ln((2H + D)/D)
Z_odd = Z₀_differential / 2
Z_even = 2 × Z₀_common
Z_differential = 2 × Z_odd
Z_common = 0.5 × Z_even
H— Height between reference planes (or height to nearest plane in asymmetric stripline)D— Diameter or width of the conductorS— Spacing between coupled tracesZ_odd— Impedance for opposite-phase signals on coupled linesZ_even— Impedance for same-phase signals on coupled linesZ_differential— Impedance measured between two differential signal linesZ_common— Impedance of common-mode currents
Key Considerations for Accurate Impedance Control
Achieving target impedance requires attention to geometry, material properties, and manufacturing tolerances.
- Dielectric constant variation with frequency — The effective dielectric constant of FR-4 and other substrates shifts with frequency, especially above 1 GHz. High-speed designs should verify that the Ɛᵣ value used matches the operating frequency range. Nanofiber or specialty laminates offer flatter frequency response than standard FR-4.
- Copper surface roughness and conductor losses — Real copper traces exhibit surface roughness that increases effective conductor thickness at high frequencies, slightly raising impedance. Very thin traces (< 3 mil width) become difficult to control precisely, introducing manufacturing yield risk. Thicker copper (2 oz or greater) eases fabrication tolerances but may require adjusted trace widths.
- Via stitching and ground plane continuity — Discontinuities in ground planes, excessive via spacing in ground stitching, and ground plane gaps beneath coupled traces degrade impedance control. Maintain ground plane continuity within at least 3× the trace width, and stitch multiple vias (every 20–30 mil) around signal transitions and differential pairs.
- Differential pair length matching and skew — For differential signaling, length skew between positive and negative traces should stay below one tenth of the bit period (or a few mils for high-speed protocols like USB 3.0 and PCIe). Unequal trace lengths introduce skew-induced jitter and degrade noise margins. Meander traces symmetrically to minimize skew while respecting spacing rules.
Practical Design Workflow and Tolerances
Impedance control is achieved through careful selection of trace geometry and laminate stack-up. Begin by selecting your target impedance (typically 50 Ω for single-ended, 100 Ω differential for digital signaling, 75 Ω for video applications) and your substrate material—FR-4 with Ɛᵣ ≈ 4.5 is standard for cost-sensitive designs.
Using this calculator, iterate on trace width and height to reach the target impedance. For a two-layer board with 1.6 mm substrate and 1 oz copper:
- 50 Ω microstrip typically requires 10–15 mil width
- 100 Ω differential (edge-coupled on surface) needs roughly 8–10 mil trace width with 10–15 mil spacing
- Tight tolerances (±5 % impedance) demand controlled depth of copper etching, uniform dielectric thickness, and careful trace width control via fabrication
Communicate your stack-up, trace geometry, and impedance requirements to your PCB fabricator. Most modern shops use automated optical inspection and can hold ±0.5 mil trace width tolerance. Specify impedance as a fabrication requirement, and request test coupons for impedance verification by TDR (time-domain reflectometry).