What is a MOSFET and How Does Threshold Voltage Matter?

A metal-oxide-semiconductor field-effect transistor (MOSFET) is a voltage-controlled semiconductor switch. Unlike bipolar transistors, which respond to input current, MOSFETs rely on an electric field to modulate conductivity in a channel between source and drain. The gate electrode, insulated by a thin oxide layer, creates this field when biased appropriately.

Threshold voltage (V_T) is the critical boundary: when gate-source voltage exceeds V_T, the channel inverts and charge carriers (electrons in n-channel devices, holes in p-channel) accumulate in sufficient density to conduct current. Below V_T, the channel remains depleted and the device blocks current. This binary switching behaviour underpins modern digital and analog electronics.

Operating Regions and the Role of Threshold Voltage

MOSFET behaviour divides into three regimes, all defined relative to V_T:

  • Cutoff: V_GS < V_T. Channel is fully depleted; only leakage current flows (typically nanoamperes).
  • Triode (Ohmic): V_GS ≥ V_T and V_DS is small. The channel acts as a voltage-controlled resistor, with on-resistance inversely proportional to (V_GS − V_T).
  • Saturation: V_GS ≥ V_T and V_DS is large. Channel pinches off near the drain; current depends on (V_GS − V_T)² and is nearly independent of V_DS.

Accurate V_T prediction ensures correct biasing, prevents unexpected leakage, and optimizes switching speed and power efficiency.

Calculating Threshold Voltage

Threshold voltage depends on fabrication geometry and doping profile. The unperturbed threshold voltage V_T0 (gate voltage relative to substrate) is derived from oxide capacitance, silicon permittivity, substrate doping, and surface potential:

V_T0 = (√(2·ε_Si·q·N_A·(2·φ_F))) / C_ox − 2·φ_F

γ = √(2·ε_Si·q·N_A) / C_ox

V_T = V_T0 + γ·(√(2·φ_F + V_SB) − √(2·φ_F))

  • ε_Si — Absolute permittivity of silicon (product of relative permittivity and vacuum permittivity).
  • q — Elementary charge (1.602 × 10⁻¹⁹ C).
  • N_A — Substrate doping concentration (cm⁻³).
  • C_ox — Oxide capacitance per unit area (F/cm²).
  • φ_F — Fermi surface potential, derived from intrinsic carrier concentration and temperature.
  • γ — Body effect coefficient; determines how V_SB shifts V_T.
  • V_SB — Source-body voltage; zero for conventional substrate connection, non-zero when source and substrate are separated.

Key Considerations for Threshold Voltage Design

Accurate V_T prediction requires careful attention to several physical and environmental effects.

  1. Temperature Dependence — Threshold voltage decreases approximately 2 mV/°C for typical CMOS processes. In high-temperature operation or automotive environments, account for V_T reduction to prevent unexpected channel leakage or delayed switching response.
  2. Body Effect Shifts — When source and substrate potentials differ, the body effect coefficient γ modulates V_T upward. In modern integrated circuits, multiple substrate bias domains create distinct V_T values for different cells. Overlooking body effect can cause timing violations or excessive standby current.
  3. Oxide Thickness Variation — Ultrathin oxides (≤2 nm) exhibit quantum mechanical effects and direct tunnelling that classical oxide capacitance models may underestimate. For advanced nodes, include oxide-layer physical modelling or consult SPICE parameters from your foundry.
  4. Doping Profile Gradients — Simple calculations assume uniform doping; realistic substrates feature channel doping implants and retrograde profiles. Non-uniform doping shifts the effective surface potential and V_T, especially in short-channel devices where source-drain fields penetrate deeper into the bulk.

Understanding the Body Effect

In typical circuit layouts, source and substrate are not at the same potential. When V_SB > 0 (source voltage above substrate), the substrate-channel junction reverse-biases, reducing inversion charge density and raising V_T. This is the body effect.

The body effect is captured by the coefficient γ (gamma), which depends on oxide capacitance and doping. As V_SB increases, the term √(2·φ_F + V_SB) grows faster than √(2·φ_F), causing V_T to increase. Typical γ values range from 0.3 to 0.7 V^{0.5} in modern CMOS.

Understanding body effect is essential for multi-threshold-voltage cell libraries (HVT, SVT, LVT), where different substrate potentials yield different operating points for the same device geometry.

Frequently Asked Questions

What physically happens at the threshold voltage?

At V_GS = V_T, the Fermi level at the oxide-silicon interface aligns with the intrinsic level. Thermal generation of electron-hole pairs in the surface region becomes sufficient to accumulate electrons (in n-channel) to a density matching the bulk hole concentration. Below this point, the surface is p-type (depleted); above it, the surface becomes n-type (inverted). The crossover marks the onset of conduction.

Why does threshold voltage depend on substrate doping?

Higher substrate doping (N_A) increases the depletion-layer width and the surface potential needed to invert the channel. The body effect coefficient γ scales with √(N_A); heavier doping requires larger gate-source voltage to accumulate sufficient channel charge. This is why high-voltage devices with lightly doped substrates have lower V_T than standard low-voltage CMOS.

How does temperature affect threshold voltage and circuit performance?

V_T decreases with temperature at approximately −2 mV/°C for bulk CMOS. Simultaneously, charge-carrier mobility also drops, slowing switching speed. These competing effects mean circuits designed at nominal temperature may become unreliable at extremes: cold operation risks timing failures (slower switching), while hot operation risks leakage and marginal gate control. Timing closure requires analysis across the full temperature range.

Can I measure threshold voltage directly, or must I calculate it?

Both approaches are valid. Calculation from oxide capacitance, doping, and surface potential gives V_T0 (zero body bias). Measurement involves biasing gate and substrate at different potentials and detecting the drain-source current inflection point; this directly yields actual V_T including body effect. Measurement is preferred for validation because it captures real on-chip variability and parasitic effects that analytical models may miss.

What is the difference between V_T0 and V_T?

V_T0 is the unperturbed threshold voltage, defined with the substrate and source at the same potential (V_SB = 0). V_T is the actual threshold voltage accounting for non-zero source-body voltage. The body effect coefficient γ couples them: V_T = V_T0 + γ·(√(2·φ_F + V_SB) − √(2·φ_F)). In modern designs with multiple bias domains, V_T values vary spatially across the chip; designers must track both quantities.

Why do 5 V logic MOSFETs typically have V_T between 0.7 and 1.0 V?

This range balances competing requirements. Higher V_T reduces leakage and improves noise margins but slows switching and increases power supply overhead. Lower V_T speeds up circuits but permits greater off-state leakage. At 5 V supply, V_T ≈ 0.8 V provides reasonable margin above ground (0 V) while remaining well below supply, ensuring good control of current in both triode and saturation. Modern sub-micron processes use lower V_T (0.3–0.6 V) because lower supply voltages and tighter integration favour speed over leakage (mitigated by power gating).

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